1. Field of the Invention
The invention relates to an integrated memory circuit having a memory cell array and a repair circuit for repairing a single bit error. The invention furthermore relates to a method for repairing a single bit error in an integrated memory circuit.
2. Description of the Related Art
Memory cells of integrated memory circuits, in particular of DRAM memory circuits, may be subject to degradation if they are exposed to method steps with high temperatures, such as may occur for example during packaging or soldering. It can happen, therefore, that in the case of previously tested and error-free memory circuits, after assembly to form a module, memory cells fail and single bit errors thereby occur which render the module unusable and have a considerable effect on the yield in the production of memory modules. Such memory modules are therefore repaired by means of a repair circuit, these then being programmed manually with the aid of an electrical fuse and subsequently being tested anew. The repair with the aid of an electrical fuse is carried out by means of an external access. The repair usually requires a renewed test, the storage of an error address in an error address memory and the subsequent repair by writing to the fuse in order to repair the defective memory cell determined previously. This procedure is complicated and represents a considerable cost factor in the production of a memory module having a plurality of memory circuits.